Fortinet
Principal ASIC Designer
$192K–$235K
Sunnyvale, CA · Hybrid · Principal · Full-time · Posted Oct 23, 2026
- Experience
- 8+ years in high-performance networking or processor design.
- Education
- B.S. or M.S. in Electrical Engineering (EE), Computer Engineering (CE), Computer Science (CS), or a related technical field.
- Visa sponsorship
- Must be authorized to work in the U.S. without sponsorship.
About the job
Design and deliver next-generation AI-powered network-processing ASICs, from micro-architecture and RTL through verification, physical design, prototyping, and bring-up.
What you'll do
- Define micro-architecture, implement chip-level RTL, and integrate IP.
- Review verification plans, analyze coverage, run full-chip simulations, and support FPGA prototyping and validation.
- Collaborate on physical design and PPA optimization, timing closure, system bring-up, and post-silicon debugging.
What they ask for
- 8+ years of experience in high-performance networking or processor design.
- Track record taking complex ASIC/FPGA designs from concept to mass production.
- Hands-on Verilog / SystemVerilog HDL coding, synthesis, and design verification; strong understanding of SystemVerilog and UVM.
- Strong background in AI/LLM accelerator or NPU design.
Nice to have
- Experience with Altera (Intel) / AMD Xilinx FPGA architectures, EDA tools, and IP portfolios.
- Deep understanding of Ethernet protocols and the TCP/IP networking stack; experience in microprocessor architecture, programmable logic, or custom domain-specific accelerators.
Pay
USD $192,000-$235,000 base salary
Tools
SystemVerilog, Verilog HDL, UVM, Altera (Intel), AMD Xilinx, FPGA, Ethernet, TCP/IP
AI focus
Develop next-generation AI-powered network-processing ASIC architecture, including AI/LLM accelerator or NPU design.
Model-written summary · the original posting is authoritative