ASIC Formal Verification Engineer, TPU Compute
Sunnyvale, CA, USA · Full-time · Posted Jun 2, 2026
- Experience
- 8 years in silicon development or ASIC/SoC design; preferred: 10 years with industry-standard tools, languages, and methodologies for silicon-based ICs and chips.
- Education
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
About the job
Defines and leads formal verification for complex TPU ASIC and SoC designs, from verification planning through sign-off and silicon bringup.
What you'll do
- Define formal verification sign-off approaches and build reusable testbenches, methodology flows, and SystemVerilog Assertions suites.
- Translate specifications into verification plans and maintain CI, regression flows, dashboards, and sign-off metrics.
- Guide design and verification teams in applying formal methods.
What they ask for
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
- Experience in silicon development or ASIC/SoC design.
- Experience with SystemVerilog Assertions (SVA) and formal verification methods.
Nice to have
- Master's degree or PhD in a relevant field, emphasizing computer architecture.
- Experience with formal verification platforms, applications, arithmetic units, schedulers, NOCs, networking topologies, or AXI/AMBA protocols.
Pay
$163000 - $237000 USD base salary
Tools
SystemVerilog Assertions (SVA), Cadence Jasper, Synopsys VC Formal, Siemens Questa Formal, AXI/AMBA
AI focus
Verifies TPU architecture and its integration into AI/ML-driven systems; the ASICs accelerate data-center computation.
Model-written summary · the original posting is authoritative