ASIC Power Engineer, ML Accelerators
Sunnyvale, CA, USA · Full-time · Posted Oct 27, 2026
- Experience
- 8 years in silicon design or architecture.
- Education
- Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
About the job
Design and optimize power-efficient ASICs for Google’s TPU machine-learning accelerators, from power modeling and architecture through implementation.
What you'll do
- Build power models and drive designs toward power goals.
- Develop architectural and microarchitectural power optimizations, methodologies, and best practices.
- Collaborate with software and system teams on power-management architectures.
What they ask for
- Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
- 8 years of experience in silicon design or architecture.
- Experience with power design, power modeling, power architecture, or power reduction methodologies or techniques.
Nice to have
- Master’s degree or PhD in Electrical Engineering, Computer Engineering, or Computer Science, with an emphasis on computer architecture.
- Experience with chip-wide power-management architecture, pre- and post-silicon power modeling and measurement, or modern silicon- and system-level power and thermal management.
Pay
$163000 - $236000 USD base salary; 15% bonus target + equity + benefits (amounts not specified)
Tools
TPU, ASIC, Dynamic Voltage and Frequency Scaling (DVFS)
AI focus
Develop power-efficient TPU hardware that accelerates AI/ML applications.
Model-written summary · the original posting is authoritative