ASIC Power Manager, ML Accelerators
Sunnyvale, CA, USA · Manager · Full-time · Posted Oct 28, 2026
- Experience
- 10 years of experience with ASIC or SoC design; preferred: 5 years managing mid-sized ASIC/SOC design teams.
- Education
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience. Preferred: Master's degree or PhD in Electrical Engineering, Computer Engineering, or Computer Science, with an emphasis on computer architecture.
About the job
Leads a team designing and optimizing ASIC power architecture and power management for Google TPU designs.
What you'll do
- Manage a power design team responsible for power architecture, optimization, and system power integration.
- Lead process, method, and tool improvements to increase TPU power efficiency and drive designs toward power targets.
- Develop power optimization and management approaches with software and system teams.
What they ask for
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
- 10 years of experience with ASIC or SoC design.
- Experience with power design, power modeling, power architecture, or power reduction methodologies or techniques.
Nice to have
- Master's degree or PhD in Electrical Engineering, Computer Engineering, or Computer Science, emphasizing computer architecture.
- 5 years managing mid-sized ASIC/SOC design teams focused on power design and optimization; experience with chip-wide power management, pre- and post-silicon power modeling, or power and thermal management.
Pay
USD 192000 - 278000 (base salary)
Tools
ASIC, SoC, TPU, RTL, Dynamic Voltage and Frequency Scaling (DVFS)
AI focus
Develops power-efficient hardware acceleration and power management for TPUs that support AI/ML applications.
Model-written summary · the original posting is authoritative