Low Power Verification Engineer, Physical Design
Sunnyvale, CA, USA · Full-time · Posted Sep 23, 2026
- Experience
- 8 years required.
- Education
- Bachelor's degree in Electrical Engineering, Computer Engineering, or equivalent practical experience.
About the job
Verifies post-layout low-power implementation of Google TPU designs, including multi-voltage power integrity, physical netlists, and clock-tree behavior, through tapeout signoff.
What you'll do
- Develop and execute post-layout low-power verification methodologies for multi-voltage designs.
- Validate low-power design collateral and gate-level implementation, including power/ground integrity and UPF alignment.
- Debug physical-design, place-and-route, and clock-tree issues; refine power-state tables and UPF scripts.
What they ask for
- Bachelor's degree in Electrical Engineering, Computer Engineering, or equivalent practical experience.
- 8 years of experience in post-layout physical netlist validation and low-power signoff in advanced ASIC workflows.
- Experience with static low-power rule-checking tools such as VCLP or CLP, including debugging structural checks and signal corruption.
- Experience validating isolation cells, power switches, level shifters, retention registers, and always-on cells from synthesis through place and route.
Nice to have
- Master's degree or PhD in Electrical Engineering, Computer Engineering, or Computer Science, emphasizing computer architecture.
- Experience with Tcl or Python, P&R tools (Innovus, Fusion), UPF, or low-power architecture and verification.
Pay
$163000 - $236000 (USD) base salary
Tools
Synopsys VCLP, CLP, Unified Power Format (UPF), Tcl, Python, Innovus, Fusion, IEEE 1801 UPF
AI focus
Verifies low-power hardware for TPUs that accelerate AI/ML applications; no AI model development is stated.
Model-written summary · the original posting is authoritative