Drimva

Google

Physical Design Engineer, 3D Technology

Sunnyvale, CA, USA · Full-time · Posted Sep 29, 2026

Experience
4 years of experience with physical design and 3D integration technologies.
Education
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.

About the job

Develops 3D physical design methodologies and custom circuits for high-performance ASICs and SoCs, optimizing designs from implementation through tapeout and manufacturing.

What you'll do

  • Develop 3D technology platforms and physical design flows, including TSV methodology and verification.
  • Optimize digital blocks for performance, power, area, and reliability; investigate trade-offs across technology nodes and implementation techniques.
  • Build custom transistor- and gate-level circuits and collaborate with physical design, technology, circuits, architecture, and IP teams.

What they ask for

  • Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
  • 4 years of experience with physical design and 3D integration technologies, such as 3D-IC, 2.5D, chip stacking, vertical stacking, Integrity, or Through-Silicon Vias (TSV).
  • Experience running industry standard chip design tools, such as Synopsys, Cadence, Siemens EDA/Mentor Graphics.

Nice to have

  • Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
  • Experience with PPA trade-offs, advanced FinFET/GAA nodes, product tapeouts, design-flow scripting, or standard-cell, SRAM, power, noise, and IR analysis.

Pay

$138000 - $197000 (USD) base salary

Tools

ASIC’s, SoC’s, 3D-IC, 2.5D, Integrity, Through-Silicon Vias (TSV), Synopsys, Cadence

AI focus

Develops TPU hardware and 3D physical design technology supporting AI/ML acceleration.

Model-written summary · the original posting is authoritative

First seen Oct 21, 2026 · Last verified Nov 4, 2026 (UTC)