Physical Design Lead, Static Timing Analysis
Sunnyvale, CA, USA · Full-time · Posted Oct 19, 2026
- Experience
- 10 years in STA, including 5 years in technical leadership; preferred: 12 years in STA and 5 years leading STA activities for SOC.
- Education
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
About the job
Leads static timing analysis and timing closure for complex, high-performance ASICs, including Google TPU physical implementation and sign-off.
What you'll do
- Lead timing constraint creation and validation, timing analysis, engineering change orders, and final timing sign-off.
- Develop and execute STA methodologies and implementation flows using industry-standard timing and parasitic extraction tools.
- Collaborate with RTL design, DFT, and other teams to resolve technical issues and deliver high-quality integrations.
What they ask for
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
- 10 years of experience in static timing analysis, including 5 years in a technical leadership capacity.
- Experience achieving full-chip timing convergence and authoring, reviewing, or validating timing constraints.
- Experience with Tcl, EDA tools, and analysis of cross-chip clock distribution networks.
Nice to have
- Master's degree or PhD in Electrical Engineering, Computer Engineering, or Computer Science, with an emphasis on computer architecture.
- Experience leading physical design or STA methodology to successful tape-outs and shipped silicon.
Pay
$192000 - $278000 USD base salary
Tools
Tcl, Synopsys Design Constraints (SDC), PrimeTime, Tempus, Timevision, STAR-RC
AI focus
Works on TPU hardware acceleration that powers AI/ML applications; the role focuses on STA and physical implementation rather than AI model development.
Model-written summary · the original posting is authoritative