Senior ASIC Design Verification Engineer, Cloud
Sunnyvale, CA, USA · Senior · Full-time · Posted Oct 12, 2026
- Experience
- 8 years of experience with design verification; preferred: 10 years with industry standard tools, languages and methodologies relevant to silicon-based ICs and chips.
- Education
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
About the job
Verify complex digital ASIC designs for Google's data-center TPUs, including verification planning, coverage closure, debugging, and support for silicon bring-up.
What you'll do
- Plan verification scenarios for complex digital design blocks with design engineers.
- Create constrained-random verification environments and coverage measures using SystemVerilog and UVM.
- Debug tests, close coverage gaps, and support functionally correct designs through tape-out.
What they ask for
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
- 8 years of experience with design verification.
- Experience verifying digital logic at RTL using SystemVerilog/UVM for ASICs.
Nice to have
- Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
- 10 years of experience with industry standard tools, languages and methodologies relevant to silicon-based ICs and chips; full verification life cycle; or three or more SoC projects/cycles and interconnect IP verification.
Pay
$163000 - $236000 USD base salary
Tools
SystemVerilog, UVM, ASICs, RTL, TPU
AI focus
Verify TPU hardware acceleration for AI/ML applications and systems.
Model-written summary · the original posting is authoritative