Senior ASIC Physical Design Engineer
Sunnyvale, CA, USA · Senior · Full-time · Posted Oct 13, 2026
- Experience
- 7 years of physical design experience.
- Education
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
About the job
Performs physical design and RTL-to-GDS closure for complex ASIC blocks and full-chip designs, optimizing power, performance, and area for Google's TPU hardware.
What you'll do
- Participate in physical design of complex blocks and contribute to full-chip and block closure from RTL-to-GDS.
- Collaborate with logic and internal and external teams on power/performance analysis and optimization.
- Conduct feasibility studies for new microarchitectures and optimize runs for finished RTL.
What they ask for
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
- 7 years of experience with physical design, including stages such as floorplanning, place and route, and timing closure.
- Experience in Python, Tcl, or Perl scripting.
Nice to have
- Experience with external partners on physical design closure, static timing analysis, Synopsys/Cadence PnR tools, backend flows, DFT, or PPA trade-offs.
Pay
USD 163000 - 236000 base salary
Tools
Python, Tcl, Perl, Synopsys/Cadence PnR tools, RTL-to-GDSII
AI focus
Contributes to physical design of TPU silicon that accelerates AI/ML applications.
Model-written summary · the original posting is authoritative