Senior CPU RTL Engineer, Silicon
Mountain View, CA, USA +2 · Senior · Full-time · Posted Oct 9, 2026
- Location
- Mountain View, CA, USA
Portland, OR, USA
Austin, TX, USA - Experience
- 8 years.
- Education
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
About the job
Designs CPU microarchitecture and RTL for next-generation processors, balancing performance, power, and area goals.
What you'll do
- Develop CPU frontend microarchitecture and RTL designs; propose and evaluate performance-enhancing features with architects and performance teams.
- Communicate trade-offs and support decisions on microarchitecture enhancements.
- Deliver production-quality designs that meet PPA goals and contribute to performance modeling for a processor functional block.
What they ask for
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
- 8 years of experience with digital logic design principles, RTL design concepts, and languages such as Verilog or SystemVerilog.
- Experience with logic synthesis techniques to optimize RTL code, performance, and power, and with low-power design techniques.
Nice to have
- Master's degree or PhD in Electrical Engineering, Computer Engineering, or Computer Science, with an emphasis on computer architecture.
Pay
$163000 - $236000 (USD) base salary
Tools
Verilog, SystemVerilog
Model-written summary · the original posting is authoritative