Senior RTL Design Engineer, TPU
Sunnyvale, CA, USA · Senior · Full-time · Posted Oct 8, 2026
- Experience
- 8 years of experience in ASIC design.
- Education
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
About the job
Design and verify SoC-level RTL for Google TPU data center accelerators, with a focus on management and control subsystems and their integration.
What you'll do
- Create and review management and control subsystem design microarchitecture specifications; implement ASIC logic in SystemVerilog RTL.
- Work with architecture and power teams to evaluate features, and with design validation teams to plan verification and debug RTL.
- Coordinate with physical design teams to meet physical requirements and achieve timing closure.
What they ask for
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
- 8 years of experience in ASIC design.
- Experience with SystemVerilog/RTL coding.
- Experience with scripting languages such as Tcl, Python or Perl.
Nice to have
- Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, emphasizing computer architecture.
- Experience with cross-functional teams, chip management, clocking, reset, I2C, SPI, UART, and digital design fundamentals.
Pay
$163000 - $236000 USD base salary
Tools
SystemVerilog, RTL, Tcl, Python, Perl, I2C, SPI, UART
AI focus
Develops TPU hardware acceleration for AI/ML applications; the role designs and verifies RTL for data center accelerators.
Model-written summary · the original posting is authoritative