Senior Staff CPU Cache Subsystem Design Engineer
Austin, TX, USA +3 · Senior Staff · Full-time · Posted Oct 13, 2026
- Location
- Austin, TX, USA
Mountain View, CA, USA
Portland, OR, USA
Poughkeepsie, NY, USA - Experience
- 15 years.
- Education
- Master’s degree in Electrical Engineering, Computer Science, or equivalent practical experience.
About the job
Leads CPU subsystem design, focusing on microarchitecture and RTL for load-store units and cache systems, from design planning through productization.
What you'll do
- Lead digital design engineers developing CPU functional units, microarchitecture, and RTL.
- Coordinate trade-off studies and design reviews with architecture, software, performance, verification, physical design, and power teams.
- Plan milestones and optimize subsystem designs to meet performance, power, area, and schedule targets.
What they ask for
- Master’s degree in Electrical Engineering, Computer Science, or equivalent practical experience.
- 15 years of experience in high-performance CPU design, including load-store unit logic/RTL, L2/L3 private/shared caches, microarchitecture definition, and PPA optimizations.
- Experience leading technical teams designing modern, high-speed, low-power processor subsystems.
- Experience with front-end quality checks such as Lint and CDC/RDC.
Nice to have
- Experience with ARM instruction set architecture.
- Experience with mobile CPU subsystems or mobile SOC architecture/integration.
Pay
USD 240000 - 333000 base salary
Tools
RTL, Lint, CDC/RDC, ARM
Model-written summary · the original posting is authoritative