Senior Static Timing Engineer
Sunnyvale, CA, USA · Senior · Full-time · Posted Sep 28, 2026
- Experience
- 8 years of experience with static timing analysis.
- Education
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
About the job
Performs static timing analysis and timing closure for high-performance ASICs, developing constraints and automation and overseeing final timing sign-off.
What you'll do
- Perform full-chip static timing analysis, create timing ECOs, and complete final timing sign-off for ASIC tape-outs.
- Debug timing and design-rule issues and develop and verify timing constraints.
- Maintain PrimeTime STA flows and build automation scripts using Perl, Python, Tcl, or Bash.
What they ask for
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
- 8 years of experience with static timing analysis.
- Experience with PrimeTime or Tempus Tcl scripting and static timing analysis debug.
- Experience with full-chip timing sign-off criteria and overseeing final ASIC timing sign-off.
Nice to have
- Master's degree or PhD in Electrical Engineering, Computer Engineering, or Computer Science, with an emphasis on computer architecture.
- Experience with complex Tcl constraints, QoR metrics and data trends, multiple foundries, or semiconductor device physics.
Pay
$163000 - $236000 USD base salary
Tools
Primetime, Tempus, Tcl, Perl, Python, Bash
Model-written summary · the original posting is authoritative