Silicon Engineer, Physical Verification, DeepMind
Mountain View, CA, USA · Full-time · Posted Oct 5, 2026
- Experience
- 8 years or more in ASIC physical verification, including production chips; experience with successful tape-outs at different hierarchy levels.
- Education
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
About the job
Leads physical verification automation and sign-off convergence for custom, high-performance chips, including floorplanning, IP integration, and tape-out readiness.
What you'll do
- Automate and integrate physical verification checks and develop a “correct by construction” methodology from design planning and floorplan.
- Plan and implement pad-rings, bumps, RDL, and IP integration.
- Collaborate across physical design, circuits, technology, and packaging teams to drive sign-off convergence and develop software for verification automation.
What they ask for
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
- 8 years or more of experience in ASIC physical verification, including production chips.
- Experience with successful chip tape-outs at multiple hierarchy levels, from block to subchips and chip-top.
- Experience with industry-standard EDA physical verification tools and software development in programming languages such as Python, C++, or Go.
Nice to have
- Experience performing technical physical evaluations of vendors, process nodes, and IP.
Pay
$217000 - $236000 USD base salary; 15% bonus target (amount not stated)
Tools
Siemens Calibre, Synopsys ICV, Fusion Compiler, Cadence Innovus, Python, C++, Go
Model-written summary · the original posting is authoritative