Silicon Engineer, Power Analysis, DeepMind
Mountain View, CA, USA · Full-time · Posted Sep 29, 2026
- Experience
- 7 years in ASIC power analysis and optimization, including production chips.
About the job
Develops and integrates automated power-analysis and optimization solutions for Google custom silicon, from SoC architecture through sign-off.
What you'll do
- Architect power solutions and establish block- and chip-level power budgets.
- Automate and integrate power-analysis and optimization processes, including RTL analysis, IP selection, physical design, and timing closure.
- Partner across teams to define power-reduction methods and manage power-management IP requirements, integration, and post-silicon validation.
What they ask for
- ASIC power analysis and optimization experience, including production chips.
- Experience with chip tape-outs and collaboration with silicon foundries and external vendors.
- Verilog and industry-standard EDA tools for power analysis and optimization.
- Scripting for flow automation and software development experience.
Nice to have
- Master's degree or PhD in Electrical Engineering, Physics, or a related field.
Pay
$217000 - $236000 (USD) base salary; 15% bonus target
Tools
Verilog, PP-RTLA, PowerArtist, PrimeTime-PX, PrimeTime, Cadence Innovus, Synopsys Fusion Compiler, Perl
Model-written summary · the original posting is authoritative