SoC DFT Engineer, Cloud
Sunnyvale, CA, USA · Full-time · Posted Oct 8, 2026
- Experience
- 5 years required; 10 years preferred.
- Education
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
About the job
Defines, implements, and verifies design-for-test strategies and circuitry for SoCs, including Google TPU silicon, and supports test, debug, quality, and yield.
What you'll do
- Develop DFT strategy, architecture, test sequences, and system-level test strategy.
- Implement and verify DFT circuitry, including scan chains, DFT compression, Logic BIST, TAP controllers, and MBIST.
- Develop diagnostic resources to debug logic and memory failures and resolve test-rule violations.
What they ask for
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
- 5 years of experience in DFT architecture, implementation, and verification for SoCs.
- Experience in silicon bring-up, debug, or validation of DFT features.
- Experience with industry-standard test methodologies and platforms, such as ATE, MBIST, JTAG, or System Level Test (SLT).
Nice to have
- Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
- Experience with fault models, DFT flows, EDA tools, or test standards and formats.
Pay
$163000 - $236000 (USD) base salary
Tools
TPU, Scan, MBIST, ATPG, JTAG, iJTAG, ATE, System Level Test (SLT)
AI focus
The role develops and tests DFT for TPU hardware that accelerates AI/ML applications.
Model-written summary · the original posting is authoritative