Staff ASIC Power Engineer, ML Accelerators
Sunnyvale, CA, USA · Staff · Full-time · Posted Oct 5, 2026
- Experience
- 10 years of experience in design or architecture.
- Education
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
About the job
Leads power modeling and optimization for Google TPU designs, developing low-power architectures and techniques to meet dynamic power targets.
What you'll do
- Build power models and drive designs toward power targets; investigate and deploy architectural and microarchitectural power optimizations.
- Define low-power RTL best practices and collaborate with software and system teams on power management architectures.
- Lead an experienced power team and own complex technical projects through delivery.
What they ask for
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
- 10 years of experience in design or architecture, such as logic design, power architecture, performance, or SoC design.
- Experience with power design, power modeling, power architecture, or power reduction methodologies or techniques.
Nice to have
- Master's degree or PhD in Electrical Engineering, Computer Engineering, or Computer Science, emphasizing computer architecture.
- Experience with chip-wide power management, pre- and post-silicon power modeling and correlation, technical leadership, or silicon- and system-level power and thermal management.
Pay
$192000 - $278000 USD (base salary)
Tools
TPU, RTL, Dynamic Voltage and Frequency Scaling (DVFS)
AI focus
Develops power models and optimization techniques for TPUs that support AI/ML applications.
Model-written summary · the original posting is authoritative