Staff ATE Test Engineer
Sunnyvale, CA, USA · Staff · Full-time · Posted Oct 16, 2026
- Experience
- 10 years in test engineering, product engineering or silicon quality/reliability.
- Education
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
About the job
Leads silicon test strategy and the end-to-end ATE test lifecycle for Google TPU and data-center SoCs, optimizing test quality, coverage, performance, and manufacturing yield.
What you'll do
- Define silicon test requirements and align design teams, DFT engineers, and vendors.
- Lead SoC NPI, bring-up, verification, characterization, qualification, and resolution of test and correlation issues.
- Set ATE technical standards and optimize production testing, analytics, test time, yield, and RMA failure analysis.
What they ask for
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
- 10 years of experience in test engineering, product engineering or silicon quality/reliability.
- Experience in ASIC or SoC test development, bring-up or debug.
Nice to have
- Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
- Experience with scan/ATPG or memory BIST; specified IP testing; ATE probe card or load board design; UCIE, HBM, PCIE, DDR; or Advantest and Teradyne ATE.
Pay
$192000 - $278000 (USD) base salary
Tools
TPU, ASIC, SoC, ATE, scan/ATPG, memory BIST, Advantest, Teradyne
AI focus
Supports TPU hardware acceleration for AI/ML systems; the role focuses on silicon test and manufacturing, not AI model development.
Model-written summary · the original posting is authoritative