Staff SWE, ML Compiler Performance Engineer Co-Design
Mountain View, CA, USA · Staff · Full-time · Posted Sep 21, 2026
- Experience
- 8 years programming; 5 years testing and launching software products; 5 years in performance, large-scale systems data analysis, visualization tools, or debugging; 3 years in software design and architecture.
- Education
- Bachelor's degree or equivalent practical experience.
About the job
Define how open-source ML models and agentic workloads map to TPU hardware, and deliver pre-silicon performance benchmarks and reference implementations to guide optimization and planning.
What you'll do
- Set strategy and methodology for analyzing performance gaps across open-source model families and adapting models for TPU.
- Deliver pre-pilot performance benchmarks and optimize models, workflows, and kernels under compiler constraints.
- Partner with TPU Hardware, XLA Compiler, and Cloud AI Systems leadership on multi-year roadmaps.
What they ask for
- Bachelor's degree or equivalent practical experience.
- 8 years of experience programming in C++ or Python.
- 5 years of experience testing and launching software products.
- 5 years of experience with performance, large-scale systems data analysis, visualization tools, or debugging; 3 years of experience with software design and architecture.
Nice to have
- Proficiency in ML workload performance modeling, compiler representations, ML execution frameworks, or accelerator kernel programming.
- Experience architecting or extending performance simulation or modeling tools, and leading complex cross-organizational technical initiatives.
Pay
$207000 - $300000 (USD) base salary
Tools
C++, Python, PyTorch, JAX, Pallas, MLIR, XLA, CUDA
AI focus
Optimize open-source ML models, multi-turn agentic workflows, reasoning loops, and prompt/decode topologies for TPU performance before silicon tape-out.
Model-written summary · the original posting is authoritative