TPU Hardware Design Engineer, Cloud
Sunnyvale, CA, USA · Full-time · Posted Oct 1, 2026
- Experience
- 4 years of RTL design required; 5 years preferred.
- Education
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
About the job
Design and integrate microarchitecture and SystemVerilog RTL for on-chip network blocks in next-generation TPUs, Google’s AI and machine-learning accelerators.
What you'll do
- Define TPU microarchitecture and develop performant, power-efficient RTL.
- Partner with Verification and Validation teams on test plans, RTL debugging, functional correctness, and post-silicon validation.
- Collaborate with Physical Design and other partner teams on design constraints and integration.
What they ask for
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
- 4 years of experience in RTL design.
- Experience with digital design and microarchitecture design.
- Experience optimizing designs for performance, power, and area.
Nice to have
- Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
- Experience with scripting languages (i.e., Python or Perl), Linting, CDC, RDC, LEC, ASIC synthesis flows, or cross-functional work with DV and PD teams.
Pay
USD 138000 - 197000 base salary; 15% bonus target + equity + benefits (amount not specified)
Tools
SystemVerilog, Python, Perl, Linting, Clock Domain Crossing (CDC), Reset Domain Crossing (RDC), Logic Equivalence Check (LEC), ASIC synthesis flows
AI focus
Design hardware acceleration for AI/ML workloads, specifically TPU architecture and RTL for AI accelerators.
Model-written summary · the original posting is authoritative