TPU RTL Design Engineer, Google Cloud

What you'll do

• Create and review clock-control subsystem microarchitecture specifications and develop synthesizable SystemVerilog RTL for ASIC products.
• Coordinate with architecture, power, design validation, and physical design teams to evaluate features, verify RTL, and meet physical and timing requirements.
• Contribute to SoC infrastructure and methodology, including error handling, debug, chip management, and chassis components.

What they ask for

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
• 2 years of experience in ASIC RTL design focused on clocking, reset, or timing-critical RTL development.
• Experience with SystemVerilog for microarchitecture specifications and synthesizable RTL.
• Experience using Python, Tcl, or Perl for automation and data analysis, and industry-standard EDA tools for simulation, synthesis, and power analysis.

Nice to have

• Master's degree or PhD in Electrical Engineering, Computer Engineering, or Computer Science, with an emphasis on computer architecture.
• Experience with high-performance ASIC design, clocking technologies, low-power SoC optimization, or processor and accelerator design.

Pay

$138000 - $197000 USD base salary

Tools

TPU, SystemVerilog, Python, Tcl, Perl, ASIC, EDA tools

AI focus

Design hardware acceleration technology for AI/ML applications, including TPU clock-control and SoC infrastructure.