HPE
ASIC Design Engineer 2
$106K–$214K
Sunnyvale, California, United States of America · Full-time · Posted Aug 26, 2026
- Education
- Bachelor’s degree in Electrical Engineering required; Master’s degree strongly desired.
About the job
Design and develop high-speed networking ASICs, from module specifications through RTL, verification support, and timing closure.
What you'll do
- Translate functional specifications into detailed micro-architecture specifications and code RTL.
- Write functional coverage and SVA, and debug block issues identified by verification.
- Work with physical design to identify timing paths and fix RTL timing to meet frequency targets; use EDA tools for design checks.
What they ask for
- Bachelor’s degree in Electrical Engineering.
- Strong analytical and problem-solving skills; coursework in digital logic design.
- Strong Verilog/System Verilog coding skills demonstrated through courses and internship projects.
Nice to have
- Master’s degree.
- Knowledge of Computer Architecture, networking protocols, machine learning, Perl, or Python.
Pay
USD 105,500 - 213,500 (base salary)
Tools
System Verilog, Verilog, SVA, EDA tools, Perl, Python
Model-written summary · the original posting is authoritative