HPE
ASIC Verification Engineer
$106K–$243K
Durham, North Carolina, United States of America · Full-time · Posted Sep 20, 2026
- Experience
- 4+ years of experience in ASIC/SoC verification.
- Visa sponsorship
- US Citizenship Preferred.
About the job
Verifies networking ASICs and SoCs, driving block or subsystem verification from test planning through coverage closure.
What you'll do
- Develop and maintain UVM verification environments and perform constraint-driven random testing, coverage analysis, and assertion checks.
- Analyze simulations and debug complex designs using simulation tools and waveforms.
- Collaborate with cross-functional teams to resolve issues and deliver high-quality ASIC/SoC designs.
What they ask for
- Strong expertise in SystemVerilog and UVM, including developing verification environments from scratch.
- Deep understanding of randomization, constraints, functional coverage, and assertions (SVA).
- Hands-on experience with test planning, coverage analysis, and complex SoC debugging.
- Proficiency with industry-standard simulation tools and waveform debugging.
Nice to have
- Experience verifying networking ASICs or router datapath/control blocks; familiarity with high-speed interconnects, buffers, or scheduling pipelines.
- Exposure to emulation, hardware acceleration, traffic-model integration, CI flows, low-power (UPF), formal verification, or post-silicon bring-up and debug.
Pay
USD 105,500 - 243,000 (base salary)
Tools
SystemVerilog, UVM, Cadence Xcelium, Synopsys VCS, Mentor Questa, SVA, Jenkins, UPF
Model-written summary · the original posting is authoritative