HPE
ASIC Verification Engineer
$120K–$243K
Sunnyvale, California, United States of America · Full-time · Posted Aug 19, 2026
- Experience
- 5+ years of ASIC/SoC verification experience.
About the job
Verifies networking ASIC and SoC blocks and subsystems, from test planning through coverage closure, to ensure design functionality and delivery quality.
What you'll do
- Own verification efforts, create test plans, and achieve coverage closure.
- Develop and maintain UVM environments; run constrained-random tests and debug complex designs.
- Analyze simulations, waveforms, functional coverage, and assertions; collaborate to resolve issues.
What they ask for
- 5+ years of ASIC/SoC verification experience, owning verification from test plan to coverage closure.
- Strong SystemVerilog and UVM expertise, including developing environments from scratch.
- Understanding of randomization, constraints, functional coverage, and SVA assertions.
- Hands-on test planning, coverage analysis, complex SoC debugging, and proficiency with industry-standard simulators and waveform debugging.
Nice to have
- Experience verifying networking ASICs or router datapath/control blocks; familiarity with high-speed interconnects, buffers, or scheduling pipelines.
- Exposure to emulation, hardware acceleration, traffic-model integration, Jenkins or CI, UPF, formal verification, or post-silicon debug.
Pay
USD 120,000 - 243,000 (base salary)
Tools
SystemVerilog, UVM, Cadence Xcelium, Synopsys VCS, Mentor Questa, SVA, Jenkins, UPF
Model-written summary · the original posting is authoritative