HPE
ASIC Verification Engineer
$120K–$243K
Sunnyvale, California, United States of America · Full-time · Posted Sep 16, 2026
- Experience
- 5+ years in ASIC/SoC verification.
About the job
Verifies networking ASIC/SoC blocks and subsystems, developing UVM environments and driving testing, debug, and coverage closure.
What you'll do
- Own verification from test planning through coverage closure; develop and maintain UVM environments.
- Run constraint-driven random tests, analyze simulations and waveforms, and debug complex SoC designs.
- Collaborate across teams to resolve issues and deliver high-quality ASIC/SoC designs.
What they ask for
- Strong SystemVerilog and UVM expertise, including building environments from scratch.
- Understanding of randomization, constraints, functional coverage, and assertions (SVA).
- Hands-on test planning, coverage analysis, and complex SoC debug experience.
- Proficiency with industry-standard simulation tools and waveform debugging.
Nice to have
- Networking ASIC or router datapath/control-block verification; high-speed interconnects, buffers, or scheduling pipelines.
- Emulation, hardware acceleration, traffic-model integration, Jenkins/CI, UPF, formal verification, or post-silicon debug.
Pay
USD 120,000 - 243,000 annual base salary
Tools
SystemVerilog, UVM, Cadence Xcelium, Synopsys VCS, Mentor Questa, SVA, Jenkins, UPF
Model-written summary · the original posting is authoritative