HPE
ASIC Verification Engineer
$124K–$251K
Sunnyvale, California, United States of America · Full-time · Posted Oct 12, 2026
- Experience
- 7+ years.
About the job
Verifies networking ASIC and SoC blocks and subsystems, developing verification environments and driving test-plan execution through coverage closure.
What you'll do
- Own block-level or subsystem verification, from test plans through coverage closure.
- Develop and maintain UVM environments; perform constrained-random testing, coverage analysis, assertions, and design debug.
- Analyze simulations and waveforms, and collaborate across teams to resolve issues and deliver ASIC/SoC designs.
What they ask for
- 7+ years of ASIC/SoC verification experience, including ownership from test plan to coverage closure.
- Strong SystemVerilog and UVM expertise, including building environments from scratch.
- Deep understanding of randomization, constraints, functional coverage, and assertions (SVA).
- Hands-on test planning, coverage analysis, complex SoC debug, and proficiency with industry-standard simulation tools.
Nice to have
- Networking ASIC or router datapath/control-block verification; high-speed interconnects, buffers, or scheduling pipelines.
- Emulation, hardware acceleration, traffic models, Jenkins/CI, UPF, formal verification, or post-silicon bring-up and debug.
Pay
USD 124,000 - 251,000 base salary (annual)
Tools
SystemVerilog, UVM, Cadence Xcelium, Synopsys VCS, Mentor Questa, SVA, Jenkins, UPF
Model-written summary · the original posting is authoritative