Design Verification Manager

What you'll do

• Manage, mentor, and allocate resources for design verification engineers across parallel schedules.
• Define verification strategies, testbench architecture, infrastructure, and execution plans across block, subsystem, and full-chip environments.
• Coordinate with architecture, RTL design, physical design, and post-silicon teams to address coverage gaps, debug failures, and meet tape-out milestones.

What they ask for

• Bachelor’s degree in Electrical Engineering, Computer Science, Computer Engineering, or a closely related technical field.
• 10+ years of hands-on pre-silicon ASIC/SoC Design Verification experience.
• 5+ years of engineering management or formal team leadership directly managing engineering headcount, performance reviews, and project schedules.
• Expert fluency in SystemVerilog and UVM architecture; proven mastery of building scalable UVM-compliant testbenches from scratch.

Nice to have

• Master's degree or Ph.D. in Electrical Engineering or Computer Science; exposure to or experience applying AI/ML in verification pipelines.
• Experience with multi-protocol high-speed interfaces such as PCIe Gen6/7, CXL, HBM3, or NVLink; ability to manage globally distributed teams.

Pay

USD 174,000 - 352,500 base salary

Tools

SystemVerilog, Universal Verification Methodology (UVM), Palladium, Zebu, Veloce, PCIe Gen6/7, CXL, HBM3

AI focus

Preferred exposure to or hands-on use of AI/ML in verification pipelines, including smart stimulus generation, coverage convergence, automated bug triage, or regression optimization.