HPE
Networking Signal Integrity Engineering Manager
$183K–$390K
Sunnyvale, California, United States of America · Manager · Full-time · Posted Sep 2, 2026
- Experience
- 5+ years managing signal integrity engineers.
- Education
- B.S. Electrical Engineering minimum; M.S. Electrical Engineering preferred.
About the job
Lead a team developing PAM4 SerDes implementations and signal integrity rules for new hardware networking products.
What you'll do
- Lead SI engineers across multiple product programs and deliver high-quality work on schedule.
- Coordinate with hardware, software, PCB layout, manufacturing test, and SI management across the US and India.
- Resolve field and emergency customer escalations.
What they ask for
- 5+ years managing signal integrity engineers.
- Knowledge of PAM4 SerDes, signal integrity, clocking, and phase lock loops.
- Knowledge of SI CAD tools, including HFSS, SiWave, and Keysight ADS.
- Knowledge of SI lab equipment, including DCAX sampling scope, UXR real time scope, VNA, TDR, and Signal Source Analyzer for phase noise measurements.
Nice to have
- M.S. Electrical Engineering.
- Knowledge of Cadence Allegro and Allegro Constraint Manager.
Pay
USD 183,000 - 389,500 annual base salary
Tools
PAM4 SerDes, HFSS, SiWave, Keysight ADS, DCAX sampling scope, UXR real time scope, VNA, TDR
Model-written summary · the original posting is authoritative