HPE
Principal ASIC Design Engineer
$181K–$367K
Sunnyvale, California, United States of America · Principal · Full-time · Posted Oct 12, 2026
- Experience
- 15+ years of relevant experience.
- Education
- Bachelor’s degree in Electrical Engineering; Master’s strongly desired.
About the job
Architects and implements high-performance networking-chip modules, ensuring they meet power, area, and performance targets from specification through validation and netlist.
What you'll do
- Architect modules and subsystems, write functional and micro-architecture specifications, and implement designs.
- Develop functional coverage and SVA; optimize power and RTL timing, and collaborate with physical design and verification teams.
- Provide technical leadership and guidance to junior engineers and interns.
What they ask for
- Bachelor’s degree in Electrical Engineering.
- 15+ years of relevant experience.
- Strong Verilog/System Verilog coding skills and experience leading and implementing high-performance subsystems from specification to final netlist.
- Strong analytical and problem-solving skills; excellent written and verbal communication skills.
Nice to have
- Master’s degree.
- Knowledge of computer architecture/networking protocols, ASIC synthesis/lint tools, and Perl/Python.
Pay
USD 181,000 - 367,000 (base salary)
Tools
Verilog, System Verilog, SVA, Perl, Python
Model-written summary · the original posting is authoritative