HPE
Principal ASIC Verification Engineer
$181K–$367K
Sunnyvale, California, United States of America · Principal · Full-time · Posted Oct 12, 2026
- Experience
- 15+ years of ASIC/SoC verification experience.
About the job
Owns verification of networking ASIC/SoC blocks and subsystems, from test planning through coverage closure, and develops UVM environments to validate complex designs.
What you'll do
- Drive block-level or subsystem verification, including test plans and coverage closure.
- Develop and maintain UVM environments; perform constrained-random testing, debug designs, and meet coverage and assertion goals.
- Analyze simulation results and collaborate across teams to resolve issues.
What they ask for
- Strong expertise in SystemVerilog and UVM, including building verification environments from scratch.
- Deep understanding of randomization, constraints, functional coverage, and SVA assertions.
- Hands-on test planning, coverage analysis, and debugging of complex SoC designs.
- Proficiency with industry-standard simulation tools and waveform debugging.
Nice to have
- Experience with networking ASICs, router datapath/control blocks, or high-speed interconnects and pipelines.
- Exposure to emulation, hardware acceleration, CI flows, low-power or formal verification, or post-silicon debug.
Pay
USD 181,000 - 367,000 base salary
Tools
SystemVerilog, UVM, Cadence Xcelium, Synopsys VCS, Mentor Questa, Jenkins, UPF
Model-written summary · the original posting is authoritative