Drimva

HPE

Principal Signal Integrity Engineer – R&D Networking Platforms

$158K–$321K

Roseville, California, United States of America · Principal · Full-time · Posted Oct 19, 2026

Experience
15+ years in signal integrity, power integrity, package design, PCB design, and high-speed system architecture.
Education
Bachelor's, Master's, or PhD degree in Electrical Engineering, Computer Engineering, or related field.

About the job

Leads signal and power integrity strategy, architecture, standards, and technical decisions across HPE networking platforms from concept through production.

What you'll do

  • Set SI/PI strategy, methodologies, design standards, PCB stackup and routing guidelines, and validation approaches across networking hardware.
  • Lead architecture, reviews, complex investigations, and end-to-end electrical performance optimization with cross-functional engineering teams.
  • Develop simulation and automation methods, guide emerging technology adoption, and mentor engineers across sites.

What they ask for

  • Recognized expertise in high-speed digital design, electromagnetic theory, and advanced SerDes systems.
  • Expertise in SI/PI simulation methods and tools, including Synopsys HSPICE, Keysight ADS, Ansys HFSS, SIwave, PowerSI, and Cadence design environments.
  • Experience defining PCB stackups, routing architectures, power distribution networks, and requirements for high-volume products; hands-on laboratory instrumentation experience.
  • Ability to correlate simulations with lab measurements and lead SI/PI strategies across multiple large-scale product developments.

Nice to have

  • Technical leadership across geographically distributed teams and a record of mentoring engineers.
  • Innovation through patents, publications, industry collaboration, or significant technical contributions.

Pay

USD 158,000 - 321,000 (base salary)

Tools

Synopsys HSPICE, Keysight ADS, Ansys HFSS, SIwave, PowerSI, Cadence design environments, SerDes, VNAs

AI focus

Contributes to networking infrastructure for AI through SI/PI engineering; no AI model development is stated.

Model-written summary · the original posting is authoritative

First seen Oct 20, 2026 · Last verified Nov 5, 2026 (UTC)