HPE
Senior ASIC Physical Design Engineer
$147K–$279K
Ft. Collins, Colorado, United States of America +1 · Senior · Full-time · Posted Oct 8, 2026
- Location
- Ft. Collins, Colorado, United States of America
Chippewa Falls, Wisconsin, United States of America - Experience
- Typically 6–10 years in ASIC, VLSI, or semiconductor design implementation, including relevant physical design and timing-closure experience.
- Education
- Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, Microelectronics, or a related technical field.
About the job
Performs ASIC physical design and timing closure for complex, high-performance integrated circuits, from synthesis and partitioning through implementation and signoff.
What you'll do
- Run hierarchical and full-chip static timing analysis, maintain timing constraints, and drive timing closure.
- Perform synthesis, formal verification, partitioning, floorplanning, physical design support, and ECO implementation.
- Develop automation and implementation methodologies; collaborate with cross-functional teams and mentor engineers.
What they ask for
- Bachelor’s or Master’s degree in a related technical field.
- Experience with static timing analysis, synthesis, formal verification, floorplanning, chip partitioning, or ECO implementation.
- Experience with industry-standard EDA tools such as Synopsys or Cadence tools.
- Proficiency in Perl, Python, Tcl, or similar scripting languages.
Nice to have
- Experience with hierarchical timing analysis and full-chip timing closure.
- Experience developing ASIC implementation flows, automation, and design methodologies.
Pay
USD 147,000 - 279,000 annual base salary
Tools
Synopsys Fusion Compiler, Design Compiler, PrimeTime, Formality, Cadence RTL Compiler, Genus, LEC, Perl, Python, Tcl
Model-written summary · the original posting is authoritative