HPE
Senior ASIC Verification Engineer
$158K–$321K
Sunnyvale, California, United States of America · Senior · Full-time · Posted Oct 8, 2026
- Experience
- 6-10 years of experience in VLSI design, verification, or implementation.
- Education
- Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or equivalent.
About the job
Leads ASIC/VLSI verification for complex products, developing module test plans, models, test benches, and tests, and supporting chip-level validation and team mentoring.
What you'll do
- Create functional models, SystemVerilog/UVM test benches, and tests to verify modules against detailed test plans.
- Lead and contribute to VLSI design, validation, testing, and integration; use formal verification, coverage analysis, gate simulations, and emulation.
- Collaborate with logic and software engineers to resolve bugs and support driver development; mentor junior staff.
What they ask for
- Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or equivalent.
- 6-10 years of experience in VLSI design, verification, or implementation.
- Constrained-random verification experience, including developing block-level/full-chip test benches using SystemVerilog/UVM.
- Expert knowledge of electrical engineering fundamentals, VLSI principles, digital logic, and computer architecture.
Nice to have
- Knowledge of computer architecture/networking protocols and machine learning.
- Knowledge of Perl/Python/C/C++; excellent written and verbal communication skills.
Pay
USD 158,500 - 321,000 (base salary)
Tools
System Verilog, C/C++, UVM, Perl, Python, formal verification, EDA, FPGA
Model-written summary · the original posting is authoritative