HPE
Senior Design Verification Engineer
$154K–$310K
Sunnyvale, California, United States of America · Senior · Full-time · Posted Sep 16, 2026
- Experience
- 5–8 years of professional experience in design verification of digital/mixed-signal designs.
- Education
- Bachelor's degree in Electrical Engineering, Computer Engineering, or Computer Science.
About the job
Develops and executes emulation-based verification for complex digital designs, driving functional correctness, performance validation, and coverage closure before silicon tape-out.
What you'll do
- Create verification plans and UVM/SystemVerilog testbenches; run directed and constrained-random tests and drive coverage to closure.
- Configure and use emulation platforms for system-level verification, performance validation, and early software bring-up.
- Debug design issues, support verification sign-off, and collaborate with design, architecture, validation, software, and firmware teams.
What they ask for
- Bachelor's degree in Electrical Engineering, Computer Engineering, or Computer Science.
- 5–8 years of professional experience in design verification of digital/mixed-signal designs.
- Strong SystemVerilog and UVM proficiency, with hands-on experience using emulation-based verification platforms.
- Knowledge of digital design, constrained-random verification, coverage-driven methodologies, and hardware debugging.
Nice to have
- Master's degree in Electrical Engineering, Computer Engineering, or a related field.
- Experience with networking or interface protocols, formal verification, FPGA prototyping, power-aware verification, SoC verification, or AI/ML applications and architectures.
Pay
USD 153,500 - 310,500 annual base salary (California)
Tools
SystemVerilog, UVM, Cadence Palladium, Synopsys ZeBu, Mentor Veloce, SVA, Python, Perl
AI focus
AI/ML familiarity is preferred, including experience creating Gen AI skills, marketplaces, or agentic applications.
Model-written summary · the original posting is authoritative