HPE
Senior Methodologist for AIML Enhanced Design/Verification
$174K–$352K
Sunnyvale, California, United States of America · Senior · Full-time · Posted Sep 16, 2026
- Experience
- 3–5 years of hands-on AIML experience and 5–7 years in production RTL design and verification infrastructure.
- Education
- Bachelor's degree in Electrical Engineering, Computer Engineering, or Computer Science (or equivalent); Master's or Ph.D. preferred.
About the job
Develop and execute AI/ML-enhanced design and verification methods and infrastructure to verify complex digital designs and support silicon quality from RTL through tapeout.
What you'll do
- Build and maintain AI-based agents, skills, and design/verification infrastructure using classical and generative-AI methods.
- Create or enhance UVM testbenches and verification plans, analyze failures, and work with design teams on resolution.
- Automate RTL generation from specifications and evaluate industry tools.
What they ask for
- Bachelor's degree in Electrical Engineering, Computer Engineering, or Computer Science (or equivalent).
- 3–5 years of hands-on AIML methods, concepts, and workflows for design/verification problems.
- 5–7 years of production development of RTL design and verification infrastructure.
- Strong SystemVerilog experience; understanding of digital design fundamentals and experience with industry-standard simulation tools.
Nice to have
- Master's or Ph.D. in Electrical Engineering or Computer Science.
- Experience with formal verification tools, emulation/FPGA prototyping, or relevant publications.
Pay
USD 174,000 - 352,500 (base salary)
Tools
SystemVerilog, Synopsys VCS, Cadence Xcelium, Mentor Questa, JasperGold, VC Formal, Palladium, Protium
AI focus
Create and apply classical and generative-AI agents, skills, APIs, models, and workflows for design and verification, including AI-assisted testbench development and RTL generation from specifications.
Model-written summary · the original posting is authoritative