HPE
Senior Principal ASIC Design Engineer
$181K–$367K
Roseville, California, United States of America · Principal · Full-time · Posted Oct 12, 2026
- Experience
- 15+ years of relevant ASIC design experience.
- Education
- Bachelor’s degree in Electrical Engineering or a related field; a Master’s degree is preferred.
About the job
Leads architecture, design, implementation, and delivery of high-performance networking ASIC subsystems from product requirements through final netlist and tape-out.
What you'll do
- Define subsystem architecture and specifications, and implement RTL while balancing power, area, performance, timing, and feature goals.
- Partner with verification, physical design, software, and product teams to validate designs, close timing, and deliver subsystem requirements.
- Provide technical leadership and mentoring, improve design methodologies, and champion AI-assisted design automation.
What they ask for
- Bachelor’s degree in Electrical Engineering or a related field.
- 15+ years of relevant ASIC design experience.
- Demonstrated experience architecting and implementing high-performance ASIC subsystems from specification through final netlist.
- Experience in at least two listed areas, including Ethernet standards, memory technologies, security protocols, networking and packet processing, schedulers, or queuing and memory subsystems.
Nice to have
- Master’s degree; first-authored patents in networking or computer architecture are a plus.
- Multiple high-performance ASIC tape-outs and design leadership across the ASIC lifecycle.
Pay
USD 181,000 - 367,000 (base salary)
Tools
Verilog, SystemVerilog, Perl, Python, HBM2, HBM2E, DDR4, MACsec
AI focus
Champion practical use of AI agents, AI skills, scripts, and workflow orchestration to accelerate specification development, RTL quality checks, debugging, documentation, and design closure.
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