HPE
Sr. ASIC Design Engineer
$158K–$321K
Roseville, California, United States of America · Senior · Full-time · Posted Oct 8, 2026
- Experience
- 5+ years of relevant experience.
- Education
- Bachelor’s degree in Electrical Engineering required; Master’s strongly desired.
About the job
Designs high-speed networking ASIC modules and subsystems, from functional specifications through RTL implementation, verification support, and timing closure.
What you'll do
- Develop micro-architecture specifications that meet power and area requirements, then implement designs in Verilog or System Verilog.
- Write functional coverage/SVA and collaborate with Physical Design and Verification teams to address timing and validate blocks.
- Mentor new college-grad engineers and interns.
What they ask for
- Bachelor’s degree in Electrical Engineering.
- 5+ years of relevant experience.
- Strong analytical and problem-solving skills.
Nice to have
- Master’s degree; knowledge of computer architecture/networking protocols, synthesis/lint and EDA tools, Perl/Python, or AI agentic tools.
Pay
USD 158,500 - 321,000 (base salary; annual salary, California)
Tools
Verilog, System Verilog, SVA, Perl, Python
AI focus
Experience with AI agentic tools is a plus; no specific AI development duties are stated.
Model-written summary · the original posting is authoritative