HPE
Sr. Principle VLSI/ ASIC Design Engineer
$181K–$367K
Sunnyvale, California, United States of America · Senior · Full-time · Posted Oct 27, 2026
- Experience
- Typically, 11 + or more years in ASIC, VLSI, SoC, or related hardware design.
- Education
- Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field; equivalent experience may be considered.
About the job
Leads architecture and RTL design through implementation of complex ASIC, VLSI, and SoC solutions for networking, compute, and related applications.
What you'll do
- Lead architecture exploration and define microarchitectures, methodologies, and implementation plans.
- Drive RTL design through synthesis, timing closure support, and production readiness; assess performance, power, area, and other tradeoffs.
- Provide technical leadership, conduct design reviews, collaborate across functions, and mentor engineers.
What they ask for
- Advanced knowledge of ASIC/VLSI design, digital logic, RTL design, and SoC development.
- Complex RTL development experience using Verilog, System Verilog, or comparable hardware description languages.
- Understanding of ASIC development flows, including architecture, synthesis, timing analysis, physical design interaction, and signoff.
- Strong analytical, communication, collaboration, and technical decision-making skills; ability to influence and mentor.
Nice to have
- Experience with networking ASICs, data-processing units, switching, routing, acceleration, storage, or high-performance computing architectures.
- Design verification experience is highly desirable; familiarity with verification methodologies is also preferred.
Pay
USD 181,000 - 367,000 (base salary)
Tools
Verilog, System Verilog, ASIC, VLSI, SoC
Model-written summary · the original posting is authoritative