HPR (Hyannis Port Research)
Senior Design Verification Engineer
$112K–$280K
Needham, MA +1 · Senior · Full-time · Posted Nov 27, 2024
- Location
- Needham, MA
Needham, Massachusetts, United States - Experience
- 5+ years in design verification for FPGAs or ASICs.
- Education
- BS/MS in Computer Engineering, Electrical Engineering, Computer Science, or related.
About the job
Verifies and maintains FPGA compute and networking systems for electronic trading, owning verification from planning through coverage closure.
What you'll do
- Develop and execute verification plans, testbenches, and coverage closure; collaborate with design engineers on testing.
- Create and maintain reusable SystemVerilog verification components and testbenches.
- Mentor junior engineers and improve verification processes, tools, and methodologies.
What they ask for
- BS/MS in Computer Engineering, Electrical Engineering, Computer Science, or a related field.
- 5+ years of design verification experience for FPGAs or ASICs.
- Proficiency in SystemVerilog for verification; familiarity with constrained randomization, functional coverage, and assertion-based checking.
- Experience with simulation and debugging tools (e.g., VCS, Verdi) and comfort working in Linux.
Nice to have
- Deep understanding of computer architecture and digital design; knowledge of IP, TCP, or UDP networking protocols.
- Experience with PCIe, Ethernet, and/or DDR verification; familiarity with C, Python, and/or Perl.
Pay
$112,000 to $280,000 USD annual base salary
Tools
FPGA, ASICs, SystemVerilog, VCS, Verdi, Linux, IP, TCP
Model-written summary · the original posting is authoritative