Hudson River Trading
Design Verification (DV) Engineer
$200K–$300K
Austin, TX, United States +9 · Full-time · Posted Apr 29, 2026
- Location
- Austin, TX, United States
Boulder, Colorado, United States
Chicago, Illinois, United States
London, United Kingdom
New York, NY, United States
Austin, TX, United States
Boulder, Colorado, United States
Chicago, Illinois, United States
London, United Kingdom
New York, NY, United States - Experience
- 2+ years in RTL functional verification for FPGA or ASIC.
- Education
- A bachelor’s degree in computer science, electrical engineering, or a related field.
About the job
Verify FPGA and ASIC hardware designs by building testbenches, verification environments, and tools that ensure correctness and robustness.
What you'll do
- Create testbenches, tests, and detailed verification plans; manage test suites and continuous integration.
- Debug RTL issues and collaborate with designers on project bringup and existing design debugging.
- Develop and improve open-source and internal verification tools.
What they ask for
- Professional experience in RTL functional verification for FPGA or ASIC.
- Experience collecting and analyzing code and functional coverage.
- Experience with SystemVerilog and industry-standard frameworks such as UVM.
- Experience with Python; comfortable in a Linux environment; bachelor’s degree in computer science, electrical engineering, or a related field.
Nice to have
- Familiarity with Verilator and/or Cocotb.
- C++ experience.
Pay
200,000 to 300,000 USD per year (base salary)
Tools
FPGA, ASIC, HDL, SystemVerilog, UVM, Python, Linux, Verilator
Model-written summary · the original posting is authoritative