Intel
ADCE Packaging Design Architect
$221K–$312K
US, Arizona, Phoenix +8 · Full-time · Posted Sep 11, 2026
- Location
- US, Arizona, Phoenix
US, Oregon, Hillsboro
US, Washington, Multiple Cities
US, New Mexico, Albuquerque
US, Massachusetts, Beaver Brook
US, Colorado, Fort Collins
US, California, Santa Clara
US, California, Folsom
US, Texas, Austin - Experience
- 10+ years and in-depth knowledge/background in Package, PCB design, or IC digital design.
- Education
- Ph.D./master’s in electrical engineering/ chemical engineering/ mechanical engineering or Material Science.
About the job
Leads substrate package design from concept through tape-out, optimizing layout, routing, and silicon-package-board performance while resolving design issues and documenting the work.
What you'll do
- Develop substrate designs and implement package physical layout and routing through tape-out.
- Conduct substrate fit and routing studies and collaborate with silicon and hardware teams on performance and pinout optimization.
- Define substrate design rules, review designs, resolve DRCs, and maintain product lifecycle documentation.
What they ask for
- Strong technical background in design and electrical analysis, with a solid background in semiconductor fabrication and packaging.
- Experience with design and electromagnetic simulation tools, such as Mentor, Cadence tools, SPICE, or Ansys tools.
- Experience with Cadence Allegro platform tools and/or Mentor Xpedition platform tools.
- Ph.D. or master’s in electrical engineering, chemical engineering, mechanical engineering, or Material Science.
Nice to have
- Knowledge of assembly processes, test, and characterization techniques.
Pay
$220,920.00-311,890.00 USD (target compensation; base salary or total pay not specified)
Tools
Mentor, Cadence, SPICE, Ansys, Cadence Allegro, PCB Editor, Advanced Package Designer, Sigrity
Model-written summary · the original posting is authoritative