Drimva

Intel

AI-Driven Physical Design Engineering (PhD Intern)

$142K–$142K

US, California, Santa Clara +4 · Internship · Posted Oct 9, 2026

Location
US, California, Santa Clara
US, Colorado, Fort Collins
US, Massachusetts, Beaver Brook
US, Oregon, Hillsboro
US, Texas, Austin
Education
Enrolled in a PhD program in Electrical Engineering, Computer Engineering, Computer Science, or a related field.

About the job

Develops AI/ML workflows and automation to improve physical design execution and optimize implementation of high-performance silicon.

What you'll do

  • Research and implement AI/ML methods for physical design, and develop workflows that improve design quality and reduce manual effort.
  • Build ML-powered data analysis pipelines and GNN-based systems for design decision-making.
  • Benchmark AI-driven approaches against traditional methods for PPA improvements and collaborate with AI research and design teams.

What they ask for

  • Enrolled in a PhD program in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
  • Proficiency with physical design tools for synthesis, place and route, and timing analysis.
  • Familiarity with Python or TCL for flow automation and debugging.
  • Understanding of digital design concepts and methodologies, including RTL design and verification.

Nice to have

  • Understanding of Graph Neural Networks or graph-based algorithms; knowledge of reinforcement learning concepts for design optimization.
  • Experience with data analysis tools (Pandas, NumPy, Matplotlib) and strong Python programming with ML application experience.

Pay

$141,998.00-142,002.00 USD (target compensation; base salary or total pay not specified)

Tools

Python, TensorFlow, PyTorch, TCL, Perl, Pandas, NumPy, Matplotlib

AI focus

Applies AI/ML, including GNN-based systems, to automate and optimize silicon physical design, analyze design data, and support implementation decisions.

Model-written summary · the original posting is authoritative

First seen Oct 10, 2026 · Last verified Nov 5, 2026 (UTC)