AI GPU Cache Designer

What you'll do

• Evaluate architectural trade-offs and define microarchitecture specifications; implement RTL and deliver synthesis- and timing-clean designs.
• Work with verification and physical design teams on validation, timing constraints, synthesis, timing closure, and formal equivalence checks.
• Lead post-silicon validation, debug, and performance analysis; mentor junior engineers and advance design practices.

What they ask for

• Bachelor’s degree in Electrical Engineering, Computer Engineering, or a related field, with 12+ years of RTL design experience; OR relevant master’s degree with 8+ years; OR relevant PhD with 6+ years.
• Advanced proficiency in Verilog/SystemVerilog RTL design and hands-on SoC system integration experience.
• Expertise in AXI and AHB bus protocols and embedded processor architectures; ability to address clock domain crossings, power optimization, and timing closure.
• Proficiency in scripting languages such as Python or TCL for automation and design flow customization.

Nice to have

• Knowledge of high-speed and low-power design techniques; experience in SoC multicore CPU subsystem design and GPU cache development.
• Familiarity with EDA tools such as VCS, Questa, IES, Spyglass, Xilinx Vivado, or Altera Quartus II.

Pay

$220,920.00-311,890.00 USD (target compensation; posting does not specify base salary or total pay)

Tools

Verilog, SystemVerilog, AXI, AHB, Python, TCL, VCS, Questa

AI focus

Develops cache hardware for AI SoCs, including cache microarchitecture, RTL, integration, verification, and post-silicon performance analysis.