Drimva

Intel

Back-End TD Reliability Lab Manager

$181K–$255K

US, Arizona, Phoenix · Manager · Full-time · Posted Aug 25, 2026

Experience
3+ years of engineering management experience; 2+ years of hands-on reliability stress and testing experience.
Education
Master’s degree in Electrical Engineering, Mechanical Engineering, Physics, Materials Science, or a related technical discipline.

About the job

Manages Intel’s back-end stress test and reliability laboratory, leading engineers and expanding lab capabilities to qualify and monitor emerging semiconductor packaging technologies.

What you'll do

  • Hire, coach, and develop a laboratory engineering team while leading cross-functional resolution of reliability and technology challenges.
  • Set the lab capability and capacity roadmap and implement data collection, qualification, and Reliability Quick Turn Monitoring (QTM) strategies.
  • Lead operational excellence and quality management system readiness toward ISO 17025 accreditation, including 8D/root cause analysis.

What they ask for

  • Master’s degree in Electrical Engineering, Mechanical Engineering, Physics, Materials Science, or a related technical discipline.
  • 3+ years of engineering management experience in semiconductor packaging, reliability engineering (product or process), test engineering, or validation engineering.
  • Demonstrated expertise in process qualification, reliability risk assessment, quality management systems, and quality culture development.
  • 2+ years of hands-on experience in reliability stress and testing.

Nice to have

  • Knowledge of reliability statistics and life prediction, including accelerated life testing (ALT) and sampling plans (eg AQL/SQL).
  • Experience with dynamics testing, industry stress standards such as JESD47, advanced packaging, or third-party stress lab coordination and auditing.

Pay

$180,770.00-255,200.00 USD (target compensation; posting does not specify base salary or total pay)

Tools

Reliability Quick Turn Monitoring (QTM), ISO 17025, 8D, ALT, AQL/SQL, JEDEC, JESD47

Model-written summary · the original posting is authoritative

First seen Oct 10, 2026 · Last verified Nov 5, 2026 (UTC)