Drimva

Intel

CPU Physical Design Engineer

$106K–$200K

US, Texas, Austin · Full-time · Posted Oct 29, 2026

Experience
3+ years with a bachelor's degree, or 1+ years of relevant educational or work experience with a master's degree.
Education
Bachelor's or master's degree in Electrical Engineering, Computer Engineering, or a related field.
Visa sponsorship
See Intel U.S. Immigration Sponsorship Information for Intel’s immigration sponsorship guidelines; no specific policy stated.

About the job

Implements and verifies CPU physical design flows from RTL synthesis through GDS generation, optimizing power, performance, and area.

What you'll do

  • Implement physical design and verification flows for custom CPU designs, including synthesis and GDS generation.
  • Perform signoff activities, including formal equivalence, layout and reliability verification, and timing/power integrity analysis.
  • Collaborate across engineering teams to improve CPU designs, methodologies, and automation workflows.

What they ask for

  • Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field with 3+ years of relevant experience, or a Master's degree in the same field with 1+ years of relevant educational or work experience.
  • Experience in at least one of: successful tape-out using advanced technology nodes; industry-standard EDA tools such as Synopsys and/or Cadence for physical design flows; scripting in Python, Perl, or TCL for design automation.

Nice to have

  • PhD in a listed field; physical design verification background including DRC/LVS; familiarity with advanced-node layout rules; graduate VLSI design/Computer Architecture coursework; or exposure to/coursework in AI.

Pay

$105,650.00-200,340.00 USD (target compensation; pay type not specified)

Tools

Synopsys, Cadence, Python, Perl, TCL

AI focus

Preferred qualification: exposure to or coursework in AI; no specific AI work is described.

Model-written summary · the original posting is authoritative

First seen Oct 30, 2026 · Last verified Nov 4, 2026 (UTC)