CPU Physical Design Engineer

What you'll do

• Run CPU physical design flows, including synthesis, placement and routing, clock-tree synthesis, timing analysis, and power/noise analysis.
• Perform verification and signoff, analyze results, and recommend design improvements with cross-functional teams.
• Improve physical-design methodologies and automation while working with EDA vendors.

What they ask for

• Bachelor’s in Computer Engineering, Electrical Engineering, or related field with 6+ years of relevant experience, or M.S. (or higher) in a related field with 4+ years.
• 4+ years synthesizing a digital logic block or partition; at least 1 advanced-technology tape-out.
• 4+ years using integrated-circuit design tools for synthesis, place and route, static timing analysis, and design closure; 4+ years of PV convergence, including static timing and power analysis.
• 4+ years of chip physical-design verification and TCL scripting, including formal equivalence, electrical rules, DRC/LVS, and Noise flow.

Nice to have

• 8+ years of Tape Out experience.
• Knowledge or experience in CPU-level timing analysis, RTL-to-GDS methods, physical-design practices, static timing, noise, reliability, timing constraints, and clocking collaboration.

Pay

$141,910.00-232,190.00 USD (target compensation; pay type not specified)

Tools

Synopsys, Cadence, TCL, RTL, GDS, DRC/LVS