Intel
Deep Learning Hardware Engineer
$150K–$241K
US, California, Santa Clara +1 · Full-time · Posted Oct 23, 2026
- Location
- US, California, Santa Clara
US, Oregon, Hillsboro - Experience
- Bachelor's: 3+ years; master's: 2+ years; PhD: 3+ months of educational or work experience.
- Education
- Bachelor's, master's, or PhD degree in Computer Science, Electrical Engineering, or a STEM-related field.
- Visa sponsorship
- See Intel U.S. Immigration Sponsorship Information for Intel’s immigration sponsorship guidelines.
About the job
Design and optimize next-generation NPU and AI accelerator architectures, including RTL features and hardware-software solutions for efficient AI inference.
What you'll do
- Design and evaluate neural compute architectures and RTL implementations for machine-learning workloads.
- Analyze AI models and workloads to improve performance, power efficiency, and inference execution.
- Collaborate with architecture, software, compiler, and algorithm teams on hardware-software co-design.
What they ask for
- Bachelor's in Computer Science, Electrical Engineering, or a STEM-related field plus 3+ years of relevant experience; OR master's in the same fields plus 2+ years; OR PhD in the same fields plus 3+ months of educational or work experience.
- Digital Logic Design and RTL Design using System Verilog or Verilog.
- Knowledge of AI model architectures, layers, activation functions, and neural network topologies.
- Experience with Git workflows and repositories, and optimizing AI models using techniques such as quantization, pruning, and compression.
Nice to have
- Familiarity with AI frameworks, neural computing operations, and hardware-accelerated inference techniques.
- Experience with modern deep learning topologies, computer architecture, or cross-disciplinary hardware-software collaboration.
Pay
$149,750.00-240,710.00 USD (target compensation; base salary or total pay not specified)
Tools
System Verilog, Verilog, Git, Llama, Qwen, DeepSeek, Pi0.5, OpenVINO
AI focus
Developing NPU and AI accelerator architecture and optimizing AI workloads and inference for AI PCs, Edge AI, Agentic AI, Physical AI, and multimodal foundation models.
Model-written summary · the original posting is authoritative