Intel
Design Automation Engineer (TFM/EDA)
$138K–$266K
US, California, Folsom +3 · Full-time · Posted Oct 28, 2026
- Location
- US, California, Folsom
US, Oregon, Hillsboro
US, California, Santa Clara
US, Arizona, Phoenix - Experience
- Bachelor's degree: 6+ years; Master's degree: 4+ years; PhD: 2+ years of hands-on infrastructure and DevOps experience.
- Education
- Bachelor's degree in a relevant field, or Master's degree, or PhD.
About the job
Installs, supports, and automates EDA design environments and workflows so Intel Foundry teams can develop semiconductor designs through TapeOut.
What you'll do
- Resolve design-path tool and methodology issues, and provide training and documentation for design ramp-up.
- Develop automation and integrate tools, PDKs, and methods into scalable design workflows.
- Collaborate with EDA providers and internal teams to improve workflows and provision and troubleshoot compute capacity.
What they ask for
- US citizenship and ability to obtain a US Government Security Clearance TS/SCI.
- Experience with front-end and back-end EDA tools, flows, and methodologies, including debugging.
- Knowledge of physical design optimization and TFM tools, flows, and methodologies.
- Scripting with Tcl, Perl, or Python; familiarity with Verilog/VHDL; expertise in Linux environments, including bash and tcsh.
Nice to have
- Hands-on experience installing industry-standard front-end and back-end EDA tools.
- Experience installing foundry PDKs and flows, including Cheetah, and with debugging and design automation.
Pay
$137,610.00-265,870.00 USD (annual salary)
Tools
EDA, TFM, Tcl, Perl, Python, Verilog/VHDL, Linux, Cheetah
Model-written summary · the original posting is authoritative