Intel
Design Automation Engineer (TFM/EDA)
$101K–$194K
US, California, Folsom +3 · Full-time · Posted Oct 15, 2026
- Location
- US, California, Folsom
US, Oregon, Hillsboro
US, California, Santa Clara
US, Arizona, Phoenix - Experience
- BS with 1+ years' experience or MS with 2+ years' experience in front-end and back-end design tools and flows.
- Education
- BS or MS in Electrical or Computer Engineering.
- Visa sponsorship
- US Citizenship required.
About the job
Supports and automates Intel Foundry customers’ design and compute environments, including EDA tools, flows, licenses, and PDK collateral, through tape-out.
What you'll do
- Resolve tool and methodology issues; support design ramp-up with training and documentation.
- Coordinate with EDA providers and internal teams to integrate tools and methods and ensure project needs are met.
- Create automation for environment installation and collaborate on compute capacity and debugging.
What they ask for
- US citizenship and ability to obtain a US Government Security Clearance TS/SCI.
- BS in Electrical or Computer Engineering with 1+ years' experience, or MS in Electrical or Computer Engineering with 2+ years' experience in front-end and back-end design tools and flows.
- Experience in EDA tools and methodologies, including debugging; physical design, optimization, and TFM.
- Experience with Verilog/ VHDL, Tcl, Perl, Python scripting, and Linux (bash, tcsh).
Nice to have
- Active US Government Security Clearance with a minimum of Secret level.
- Hands-on experience installing front-end and back-end EDA tools, foundry PDKs and flows, or design automation.
Pay
$100,550.00-194,270.00 USD (target compensation; pay type not specified)
Tools
EDA, PDK, Verilog, VHDL, Tcl, Perl, Python, Linux
Model-written summary · the original posting is authoritative