Intel
Design Verification Engineer
$142K–$200K
US, California, Santa Clara +1 · Full-time · Posted Oct 22, 2026
- Location
- US, California, Santa Clara
US, Texas, Austin - Experience
- 5+ years of industry experience with a bachelor’s degree, or 4+ years of relevant experience with a master’s degree; expected years are post graduation.
- Education
- Bachelor’s degree in Electrical Engineering, Computer Science, or a related field, or a Master’s degree.
About the job
Verifies Intel interconnect and chassis IPs through verification planning, reusable testbench development, simulation and formal methods, and cross-functional debug to support first-pass silicon success.
What you'll do
- Develop and execute IP- and subsystem-level verification plans and testbenches, including reusable components, constrained-random tests, and checkers.
- Analyze simulation failures, debug and drive issues to closure, and contribute to coverage planning, coverage closure, and quality signoff.
- Collaborate with architecture, design, and software teams; contribute to simulation, formal verification, and verification automation.
What they ask for
- Bachelor’s degree in Electrical Engineering, Computer Science, or a related field with 5+ years of industry experience, or a Master’s degree with 4+ years of relevant experience.
- Hands-on coding experience in SystemVerilog, C/C++, and Python, with programming fundamentals and algorithmic problem-solving skills.
- Simulation-based verification foundation in UVM/ABV, including testbench development, debugging, and coverage-driven verification; exposure to formal verification concepts.
- Hands-on use of AI-assisted development tools in daily coding, debugging, and test development; exposure to interconnects and bus protocols such as AMBA AXI/ACE/CHI, PCIe, CXL, or UCIe.
Nice to have
- Understanding of cache coherency and memory consistency models; experience with external interfaces and system integration debug.
- Experience with formal verification tools such as JasperGold or VC Formal, emulation or FPGA-based verification; exposure to RTL, physical design, CAD flows, or system IPs such as MMUs, SMMU, IOMMU, and interrupt controllers.
Pay
$141,910.00-200,340.00 USD (total compensation)
Tools
SystemVerilog, C/C++, Python, UVM/ABV, AMBA AXI/ACE/CHI, PCIe, CXL, UCIe
AI focus
Use AI-assisted development tools as part of daily workflow for coding, debugging, and test development.
Model-written summary · the original posting is authoritative